Random access memory ("RAM") cell densities have increased dramatically with each generation of new designs and have served as one of the principal technology drivers for ultra large scale integration ("ULSI") in integrated circuit ("IC") manufacturing. The area required for each memory cell in a memory array partially determines the capacity of a memory IC. This area is a function of the number of elements in each memory cell and the size of each of the elements. State-of-the-art memory cells for gigabit memory ICs have cell areas approaching 6F.sup.2, where F represents a minimum feature size for photolithographically-defined features. Static RAM ("SRAM") densities, while increasing less dramatically than densities for dynamic RAM ("DRAM") technologies, have nevertheless also increased substantially.
A traditional six-device SRAM cell contains a pair of cross-coupled inverters, forming a latch circuit having two stable states. The minimum memory cell size attainable for this type of SRAM is approximately 120F.sup.2, as described in "CMOS Technology for 1.8V and Beyond," by Jack Y.C. Sun, 1997 Int. Symp. On VLSI Tech., Syst. And Apps., Digest of Tech. Papers, pp. 293-297. Forming SRAM cells using vertical transistors allows memory cell sizes to be reduced to 32F.sup.2, because FETs having source and drain vertically aligned may be formed to be smaller than planar FETs. Achieving further size reduction requires a new mechanism of memory cell operation. For example, tunnel diodes can provide a memory function.
FIG. 1 shows an example of a current-voltage characteristic curve 2 for a two-terminal device exhibiting so-called "N-type" negative differential resistance, where the name is derived from the resemblance of the shape of the I-V curve to the shape of the letter "N." In FIG. 1, negative differential resistance exists over a voltage range delimited on one side by a peak having a peak current I.sub.P at a peak voltage V.sub.P and delimited on the other side by a valley having a valley current I.sub.V and a valley voltage V.sub.V.
Negative differential resistance phenomena are able to provide memory functions because devices exhibiting them allow either of two different, stable voltages to result in the same current through the device, e.g., voltages V.sub.L and V.sub.H at respective points 4 and 6 on the curve 2. Devices exhibiting "S-type" negative differential resistance (also named in accordance with the shape of the shape of the I-V curve) can also provide a memory function, but with two different, stable current levels being possible for a given voltage.
Base current reversal in bipolar transistors also can permit data storage. Base current reversal results when impact ionization occurring at a p-n junction between a base and a collector in the transistor generates enough minority carriers to cancel or exceed majority carrier injection from an emitter to the base. The base terminal then displays two or more stable states that do not source or sink current, and the transistor may be used to store information represented by the state of the base terminal. FIG. 2 is a graph showing a simplified current-voltage characteristic for a storage device employing base current reversal, in accordance with the prior art.
A first stable state, at a point denoted "A," where no current passes through the base terminal corresponds to a base voltage of zero volts. As base voltage is increased from zero volts, base current is initially increased also, as shown in a first portion of a current-voltage characteristic 8 (to the left of a point marked "B"). As the base voltage increases further, the number of electrons injected into the base and then diffusing into a depleted portion of the collector increases. These electrons are accelerated through the depleted portion of the collector. At the point marked "B" on the first portion 8 of the base-emitter current-voltage characteristic, holes that are created through impact ionization in the collector region and that are swept into the base begin to outnumber electrons injected from the emitter in forming a base terminal current I.sub.B. As base-emitter voltage further increases, the number of holes created by impact ionization also increases (dashed portion of trace 8) until the net base terminal current I.sub.B becomes zero at the point marked "C" in FIG. 2, at a base emitter voltage of slightly less than 0.6 volts. This portion 8 of the current-voltage characteristic corresponds to a base current flowing in a direction normally associated with a base current for a NPN bipolar transistor.
A second portion 10 of the current-voltage characteristic corresponds to base current flowing in the opposite of the direction illustrated in the first portion 8. The second portion 10 corresponds to holes being created by impact ionization at the collector-base junction of the transistor, where the holes collected by the base outnumber electrons emitted from the emitter and collected by the base. The base current becomes increasingly negative until the point marked "D" on the curve 10. At the point marked "D," electrons injected into the base from the emitter begin to dominate the base terminal current I.sub.B, and the base terminal current I.sub.B again becomes very small (dashed trace).
The base terminal current I.sub.B again becomes zero at a point marked "L" in FIG. 2, corresponding to a base-emitter voltage of about 0.9 volts. As base-emitter voltage is increased even farther, a third portion 12 of the current-voltage characteristic corresponds to a base terminal current I.sub.B flowing in the same direction as the first portion 8. The base terminal current I.sub.B then behaves conventionally with further increases in base emitter voltage.
At the points "A," "C" and "E," the net base terminal current I.sub.B is zero. Significantly, the transistor is stable at these points. As a result, opening a switch coupled to the base results in the transistor staying at one of these points and allowing a state of the transistor to be determined by measuring the base-emitter voltage, (i.e., a "read" of the data stored in the transistor).
U.S. Pat. No. 5,594,683, entitled "SRAM Memory Cell Using A CMOS-Compatible High Gain Gated Lateral BJT", issued to M.-J. Chen and T. S. Huang, describes a memory employing base current reversal for data storage. FIG. 3 is a simplified schematic diagram of a generic memory cell 14 formed from a storage device 16 and an access element 18, in accordance with the prior art. The storage device 16 is represented as a NPN bipolar transistor in FIG. 3, however, the storage device 16 may be formed from a structure corresponding to a NMOS FET and may be capable of operating as either an NPN transistor or a NMOS FET, as described in "High-Gain Lateral Bipolar Action in a MOSFET Structure" by S. Verdonckt-Vandebroek et al., IEEE Trans. El. Dev., Vol. 38, No. 11, Nov. 1991, pp. 2487-2496.
The memory cell 14 is read by turning the access element 18 ON through application of a suitable signal to a word line driver 20. A sense amplifier (not shown in FIG. 3) is coupled to the storage device 16 through a bit line 24 and the access element 18.
Data can be written to the storage device 16 by applying a write pulse to a control electrode of a bit line switch 22 and also turning ON the access element 18 as described above. The data bit to be written to the storage device 16 is coupled through the bit line switch 22 to a control electrode of the storage device 16. The access element 18 is then turned OFF, electrically isolating the storage device 16 from the bit line 24 and storing the data bit in the memory cell 14. Compact memory cells 14 drawing as little as 1 nanoampere of standby current can be designed using this approach. However, the memory cell described in U.S. Pat. No. 5,594,683 requires an area of at least 8F.sup.2.
Compact memory cells drawing as little as 1 nanoampere of standby current can be designed using this approach. Additionally, since the base current reversal mechanism requires impact ionization within the base-collector junction, voltages generally in excess of 4 volts must be applied across the memory cell for successful operation. As a result, standby power requirements are still several nanowatts per memory cell.
Tunnel diodes have also been employed to provide negative differential resistance for SRAM cell operation. U.S. Pat. No. 5,390,145, entitled "Resonance Tunnel Diode Memory", issued to Nakasha et al., describes a memory cell using pairs of GaAs tunnel diodes coupled in series and providing memory cells having an area of about 30F.sup.2. "RTD-HFET Low Standby Power SRAM Gain Cell", IEEE El. Dev. Lett., Vol. 19, No. 1 (January 1998), pp. 7-9, by J. P. A. van der Wagt et al. describes successful operation of memory cells using III-V semiconductor resonant tunnel diodes and separate read and write devices. However, GaAs devices are expensive to manufacture.
Silicon tunnel diode memories have been demonstrated where the tunnel diode draws about one nanoampere and is coupled in series with a depletion mode load device. These memories use a single read/write device, as in a conventional one-device DRAM cell. However, depletion mode load devices again require several volts to be applied across the memory cell for successful operation. As a result, several nanowatts of standby power per memory cell are still required.
There is therefore a need for a compact and robust memory cell having reduced standby power draw requirements.